CSSE232 - Computer Architecture 1 - Revision history

ScanuRag: Add note about final project being outdated

2024-10-15T18:31:12Z

Add note about final project being outdated

← Older revision		Revision as of 18:31, 15 October 2024
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	=== Final Project ===		=== Final Project ===
			Note: The final project changed substantially starting in Fall 2024. The following may no longer be relevant

	Whatever you do for your final project, avoid pipe lining at all costs. It is extremely complex and you will regret your life choices during 10th week. Also keep in mind that around Week 7 your instructor will cut the size of your memory down dramatically, so build you CPU to be able to handle that in few changes. If you end up implementing a Memory to Memory CPU, see if you can get your instructor to allow you to use 32-bit instructions. They often say yes because they know how difficult it is to do M2M without it.		Whatever you do for your final project, avoid pipe lining at all costs. It is extremely complex and you will regret your life choices during 10th week. Also keep in mind that around Week 7 your instructor will cut the size of your memory down dramatically, so build you CPU to be able to handle that in few changes. If you end up implementing a Memory to Memory CPU, see if you can get your instructor to allow you to use 32-bit instructions. They often say yes because they know how difficult it is to do M2M without it.

137.112.220.20: added link

2024-02-13T17:36:07Z

added link

← Older revision		Revision as of 17:36, 13 February 2024
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	== Class Description ==		== Class Description ==
	In Computer Architecture, you build on your skills from ECE233 to design a computer processor with a group of other students using Verilog HDL.		In Computer Architecture, you build on your skills from [[ECE233 - Introduction to Digital Systems\|ECE233]] to design a computer processor with a group of other students using Verilog HDL.
	{\| class="wikitable"		{\| class="wikitable"
	\|Reading		\|Reading

137.112.127.253: Add some more details

2024-02-13T03:45:57Z

Add some more details

← Older revision		Revision as of 03:45, 13 February 2024
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	=== Final Project ===		=== Final Project ===
	Whatever you do for your final project, avoid pipe lining at all costs. If you ~~end up implements a Memory to Memory CPU, see if you can get~~ your ~~instructor to allow you to use 32-bit instructions~~. Also keep in mind that around Week 7 your instructor will cut the size of your memory down dramatically, so build you CPU to be able to handle that in few changes.		Whatever you do for your final project, avoid pipe lining at all costs. It is extremely complex and you will regret your life choices during 10th week. Also keep in mind that around Week 7 your instructor will cut the size of your memory down dramatically, so build you CPU to be able to handle that in few changes. If you end up implementing a Memory to Memory CPU, see if you can get your instructor to allow you to use 32-bit instructions. They often say yes because they know how difficult it is to do M2M without it.

ScanuRag: Add Comp Arch page

2024-02-13T01:37:04Z

Add Comp Arch page

New page

== Class Description ==
In Computer Architecture, you build on your skills from ECE233 to design a computer processor with a group of other students using Verilog HDL.
{| class="wikitable"
|Reading
|Recommended
|-
|Homework
|
|-
|Exams
|2
|-
|Final Exam
|No
|-
|Final Project
|Yes
|-
|Flipped Classroom
|No
|}

== Advice for Students Taking CSSE232 ==

=== Final Project ===
Whatever you do for your final project, avoid pipe lining at all costs. If you end up implements a Memory to Memory CPU, see if you can get your instructor to allow you to use 32-bit instructions. Also keep in mind that around Week 7 your instructor will cut the size of your memory down dramatically, so build you CPU to be able to handle that in few changes.